module vga(
	input [7:0] ram_data,
	input  ram_clk,
	
    input           sys_clk,        
	 input           sys_rst_n,                          
    output          vga_hs,         
	 output          vga_vs,         	
	 output  [15:0]  vga_rgb          
);
//wire define
reg  [9:0] ram_cnt;
wire 	[9:0]	display_x;
wire	[7:0] display_y;
wire         vga_clk_w;                
wire         locked_w;              
wire         rst_n_w;               
wire [15:0]  pixel_data_w;          
wire [ 9:0]  pixel_xpos_w;          
wire [ 9:0]  pixel_ypos_w;          
assign rst_n_w = sys_rst_n && locked_w;
assign display_x = pixel_xpos_w;
   
//vga_pll	u_vga_pll(                  
//inclk0         (sys_clk),    
//	.areset         (~sys_rst_n),  
//	.c0             (vga_clk_w),    
//	.locked         (locked_w)
//	); 
pll_clk u_vga_clk(
.areset (~sys_rst_n),
.inclk0 (sys_clk),
.c0	(vga_clk_w),
.locked (locked_w)
);

vga_driver u_vga_driver(
    .vga_clk        (vga_clk_w),    
    .sys_rst_n      (rst_n_w),    

    .vga_hs         (vga_hs),       
    .vga_vs         (vga_vs),       
    .vga_rgb        (vga_rgb),      
    
    .pixel_data     (pixel_data_w), 
    .pixel_xpos     (pixel_xpos_w), 
    .pixel_ypos     (pixel_ypos_w)
    ); 
    
vga_display u_vga_display(
	.display_y 		(display_y),
    .vga_clk        (vga_clk_w),
    .sys_rst_n      (rst_n_w),
    
    .pixel_xpos     (pixel_xpos_w),
    .pixel_ypos     (pixel_ypos_w),
    .pixel_data     (pixel_data_w)
    );   

always @(negedge ram_clk or negedge sys_rst_n )begin
if(sys_rst_n == 1'b0) ram_cnt <= 1'b0;
else if(ram_cnt > 10'd640 ) begin
		   if(ram_data == 1'b0) ram_cnt <= 1'b0;
			else ram_cnt <= ram_cnt;
		end
else ram_cnt<=ram_cnt+1'b1;
end 
	 
ram_ip u_ram_ip(
.rdclock (~vga_clk_w),
.rdaddress (display_x),
.q (display_y),
.data (ram_data),
.wraddress (ram_cnt),
.wrclock (ram_clk),
.wren (1'b1)
);
    
endmodule 